When the matrix becomes matter
Analogue AI does not calculate like a faster GPU. It turns neural-network weights into a physical field—and makes multiplication a consequence of passing through it.
The most important thing an analogue AI chip removes is not arithmetic. It removes the trip to fetch the arithmetic’s ingredients.
Much of neural-network inference consists of taking a vector of activations and transforming it through a matrix of learned weights. Digital accelerators do this extremely well. But they still represent every weight as bits, bring those bits through a memory hierarchy, feed them to multiplier-accumulators, and move the results onward. The multiply may be cheap. Moving the operands is often not.
This is the old von Neumann separation in its most expensive modern costume: memory over here, compute over there, an immense traffic system between them. A classic energy analysis by Stanford’s Mark Horowitz showed why architects obsess over locality: in its 45-nanometer example, fetching data from off-chip DRAM cost orders of magnitude more energy than a basic arithmetic operation. The exact ratio changes with chip, memory, precision, and workload. The architectural lesson does not.
Analogue in-memory computing changes what a weight is. In a resistive crossbar, a learned number becomes the conductance of a physical device. In a photonic processor, it may become a transmission coefficient, phase shift, or optical attenuation. The model is no longer merely stored near the computation. The stored model is the computation’s medium.
One multiply, no instruction stream
Inside a resistive array, Ohm’s law performs each multiplication and Kirchhoff’s current law performs the addition. The equations are not simulated. The circuit settles into their answer.
The number becomes a device state.
Each synaptic weight is programmed as conductance. Positive and negative values usually require differential encoding or other circuit techniques; this is physical representation, not mathematical magic.
The input becomes voltage or light.
An activation vector is applied across rows. Every cross-point responds in parallel. At each junction, Ohm’s law produces a current proportional to input times stored conductance.
The wire adds the products.
Currents meet along a column and sum according to Kirchhoff’s law. Sense circuits then measure the result, usually converting it back to digital form for activation functions and the rest of the model.
The promise is real. The absolutes are not.
A matrix-vector multiply can occur in essentially constant time.
All rows and columns operate in parallel within a fixed crossbar. But a matrix larger than the physical array must be tiled across cores or time steps. Array capacitance, converters, routing, weight loading, and nonlinear layers still have latency.
Analogue chips routinely deliver hundreds or thousands of TOPS/W.
Some optical cores and scaled-system projections reach that range. Fully integrated measured chips often report tens of TOPS/W or less. “Core,” “chip,” and “system” are different energy boundaries; precision and sparsity conventions also change the number.
Old process nodes can beat leading-edge digital silicon.
Specialized analogue architectures can produce impressive efficiency on mature nodes, and working research chips exist at 40, 90, and 130 nanometers. Yet the periphery remains digital or mixed-signal, and newer nodes can still improve converters, routing, density, and control.
Neural networks simply tolerate analogue error.
Low-precision inference can be robust, but drift, programming variation, line resistance, noise, and limited converter resolution are not free. Competitive accuracy has required calibration, differential encoding, quantization, noise-aware training, and hardware-aware model mapping.
Three numbers that cannot be merged
TOPS/W looks universal but is not. These published results describe different devices, workloads, precision assumptions, and system boundaries. Their disagreement is the point.
IBM’s 14-nanometer analogue-AI chip combined 35 million phase-change-memory devices across 34 tiles and reported up to 12.4 TOPS/W, with end-to-end speech demonstrations. Nature, 2023.
An analogue optical computer paper estimated 500 TOPS/W for a future 100-million-weight, 25-module configuration consuming 800 watts. This is a system projection, not the measured efficiency of the present hardware. Nature, 2025.
A reconfigurable photonic tensor processor projected this system efficiency because DACs, ADCs, and amplifiers dominated its 2.5-watt power budget—even though the optical core was fast. Nature Communications, 2026.
Physics gives. Interfaces collect.
The analogue core’s extraordinary efficiency can be consumed by the machinery required to make it usable.
Digital data must be translated into voltages or light. Analogue results must often be sensed, amplified, and quantized. Large models must be divided among finite arrays. Intermediate activations must move between tiles. Biases, normalization, nonlinear activation functions, attention softmax, control flow, and error management remain somewhere in the system.
This does not invalidate analogue acceleration. It identifies the engineering problem. The winning architecture is unlikely to be “analogue instead of digital.” It is more likely to be a carefully partitioned mixed-signal machine that keeps weight-stationary linear algebra inside physical arrays and gives everything else to digital logic.
That is why the best published demonstrations emphasize end-to-end models, not only a beautiful crossbar primitive. IBM’s 34-tile chip demonstrated software-equivalent accuracy on a small keyword-spotting network and near-software-equivalent accuracy on a much larger speech-transcription model. NeuRRAM demonstrated fully hardware-measured accuracy comparable to four-bit software models across image, speech, and image-recovery tasks. These are system achievements because the hardware, mapping, and training were designed together.
Analogue computing makes the architecture matter more than the transistor.
That can broaden the manufacturing path. Research systems have demonstrated useful analogue or mixed-signal operations on mature process nodes, including a fully integrated 90-nanometer closed-loop accelerator reported in 2026. This is strategically interesting because mature-node production is more widely distributed and less dependent on the very newest lithography.
But “geopolitical escape hatch” goes too far. Advanced AI systems also depend on converters, digital control, memory, packaging, interconnects, fabrication yield, software, and—at scale—high-bandwidth memory. U.S. export controls explicitly target advanced-node equipment and HBM, while a Commerce Department survey shows China already has substantial capacity in mature-node analogue, discrete, and optoelectronic production. Analogue AI changes the constraint map; it does not erase it.
Digital and analogue inference
- Weight
- A number encoded in bits
- A physical state such as conductance, charge, phase, or transmission
- Matrix operation
- Scheduled multiply-accumulates in digital logic
- Parallel response of a programmed electrical or optical array
- Data movement
- Reduced through caches, SRAM, HBM, reuse, and specialized dataflows—but not eliminated
- Weights remain stationary inside compute arrays; activations and partial results still move
- Precision
- Repeatable and programmable across supported formats
- Limited by devices, noise, converters, drift, and calibration
- Latency
- Excellent throughput; affected by memory, batching, scheduling, and utilization
- Very low array latency; full-model latency depends on tiling, conversion, routing, and digital layers
- Power
- Watts to kilowatts depending on device and system
- Microwatts at tiny sensor nodes through hundreds of watts in projected large systems; no single class-wide number
- Maturity
- Industrial software stack, precision, yield, and scale
- Rapid research progress; compilation, calibration, programmability, and deployment remain active challenges
The future is not a faster imitation of the present.
Analogue AI’s deepest advantage is representational. A digital machine stores a matrix and then performs operations upon it. An analogue machine can embody the matrix so that the operation occurs when a signal enters. The multiplication becomes a property of the route.
That is immense. It is also narrower—and more interesting—than saying the speed of physics makes inference free. The core operation can approach that ideal. The future belongs to whoever learns how little machinery must be wrapped around it.